1. Technical Field
The present invention relates in general to integrated circuit technology. In particular, the present invention relates to clock generation devices, such as utilized in CMOS microprocessor integrated circuits.
2. Description of the Related Art
In the design of integrated microprocessor circuits utilizing dynamic circuits, it is highly desirable to employ circuits having low jitter. "Jitter" is a vibration or fluctuation in a signal. In integrated circuit devices in particular, jitter is often the result of supply noise and substrate noise, and is seen as short-term instabilities in either the amplitude or phase of a signal. Jitter can thus be described as uncertainty in the occurrence of a clock edge. Two types of jitter, negative jitter and positive jitter, are usually encountered in integrated circuit devices. Negative jitter is the amount of time a clock edge precedes its ideal time. Positive jitter is the amount of time a clock edge lags its ideal time. Negative jitter of clock sources detracts from the usable cycle time of microprocessor systems.
As one example of the importance of jitter, for high-resolution graphic display devices utilizing phase-locked loop designs, the jitter performance of phase-locked loops limits the system performance. (A phase-locked loop ("PLL") is a circuit or system that utilizes feedback to maintain an output signal in specific phase relationship with a reference signal.) Power-supply noise coupling is a major cause of jitter problems seen in such PLL's, especially with low-supply voltages and with multiple clock synthesizers on the same device.
The utilization of PLL's for generating microprocessor clocks is well known in the art of integrated circuit design. For PLLs located on the same chip as a high-performance microprocessor, the power supply switching noise of the digital circuits is a major noise source for output jitter. For low-power PLLs, a second jitter source is the intrinsic noise of metal-oxide silicon devices in the PLL voltage controlled oscillator. This noise can be reduced by increasing power consumption. To obtain low-voltage analog circuits, the saturation voltage of MOS devices must be reduced by utilizing wider devices, which results in a larger parasitic capacitance between the supply voltage and the analog nodes. This larger parasitic capacitance decreases the power supply noise rejection for the same current consumption. Thus, a challenge in utilizing PLL's for microprocessor clock generation is to design a PLL which combines limited jitter, low-supply voltage and low-power consumption. Despite improvements in PLL based system jitter, the above described problems present difficulties in their application.
Surface acoustic wave ("SAW") oscillators would seem attractive for PLL applications, since SAW oscillators operate at very high frequencies and are manufactured to meet precise frequency specifications, such as having jitter of only 10 picoseconds, for example. However, a conventional analog PLL includes a voltage controlled oscillator (VCO) with a relatively large jitter, such as 200 picoseconds, for example. In combining a Surface Acoustic Wave ("SAW") oscillator with a conventional PLL, the relatively the large jitter of the PLL voltage controlled oscillator adds to the much smaller jitter of the SAW.
One or more of the above referenced, copending applications discloses a SAW oscillator combined with a digital locked loop instead of the more conventional analog PLL. The term digital locked loop ("DLL"), as used to apply to the inventions disclosed herein and in the related applications, is different than a conventional DLL. Generally, the term "DLL" as used in the conventional sense and as used herein, refers to a special type of phase locked loop. Like any phase locked loop, the DLL includes circuitry for generating a periodic signal and for phase adjusting the signal based on a feedback signal. The feedback signal is derived, in part, from the periodic signal itself. In a conventional DLL there is a digital delay element within the feedback path--that is, a delay element for which the delay is adjusted in discrete steps controlled by the logical state of digital logic elements. This digital delay element is used for phase adjustment. For more background, see, for example, U.S. Pat. Nos. 5,442,776 and 5,610,548. In the DLL of the present and related inventions, the phase adjustment is controlled digitally, but not by merely varying a digital delay element.
For an on-chip clock application, the digital-locked loop incorporating a SAW oscillator, as disclosed in the above referenced co-pending application, reduces negative jitter to approximately 10 picoseconds, based on an inherent operating jitter of 0.4% for a 400 MHz machine cycle. In comparison, a conventional analog PLL has negative jitter of approximately 200 picoseconds, based on a jitter of 8% for a 400 MHz machine cycle.
Positive jitter, on the other hand, is allowed to occur infrequently for the SAW/DLL combination, even to the extent of hundreds of picoseconds. However, because the positive jitter occurs so seldom, and the fundamental frequency of the SAW oscillator may be specified with such precision, the positive jitter is of no consequence for on-chip clock sources. That is, the resulting long-term frequency of the clock is stable at 400 MHz for on-chip applications.
While replacing a conventional PLL with a SAW-based, digital-locked loop in accordance with the above referenced patent application substantially improves the jitter for an internal chip clock, nevertheless, additional problems remain for chip-to-chip interfaces. An asynchronous chip-to-chip interface would be an alternative to deal with these problems, but metastability problems of such asynchronous interfaces are conventionally solved by pipelined latches to resynchronize data. Such latches introduce extra latency which may be unacceptable.
Thus, a need exists to reduce positive jitter penalties associated with chip-to-chip paths for DLL/SAW based clocks.